1. Field of the Invention
The present invention relates to a phase-locked loop circuit adapted to produce a stable output signal having the same frequency and phase as those of an input signal.
2. Description of the Prior Art
FIG. 1 is a block diagram of a conventional phase-locked loop circuit disclosed in, for example, Takeshi Yanagisawa, "PPL (Phase-Locked Loop) Applied Circuit", General Electronics Publishing Co., Ltd. May 20, 1983, pp. 28-29. In this diagram, a phase comparator 18 receives both a rectangular signal P1 having a target frequency and a feedback signal P2. Meanwhile a frequency switching gate circuit 19 receives an output signal q of the phase comparator 18 and gate clock pulses fl and gl. Then an N-stage frequency divider 20 receives an output signal R of the frequency switching gate circuit 19, i.e. a composite signal of the gate clock pulses fl and gl, and produces an output signal P2 which is fed back to the phase comparator 18.
Now the operation of such circuit will be described below with reference to FIGS. 2 and 3. In regard to the rectangular signal P1 supplied as an input signal, the input and output of the phase comparator 18 have waveforms represented by (a) and (c) in FIG. 3 respectively. Such input and output waveforms are derived from the phase comparator 18 comprising an SR type flip-flop of FIG. 2 which is set by the rising edge of the rectangular signal P1 and is reset by the rising edge of the feedback signal P2 to consequently produce an output signal q. Denoted by .phi. in FIG. 3 is a time difference between the rising edges of the two signals.
The frequency switching gate circuit 19 selectively outputs a gate clock pulse fl of a frequency fl in response to an input level "1" or a gate clock pulse gl of a frequency gl in response to an input level "0", and then supplies the output to the N-stage frequency divider 20. Subsequently the frequency-divided signal from the N-stage frequency divider 20 is partially returned as a feedback signal P2 to the phase comparator 18. That is, the phase difference between the input signal P1 and the feedback signal P2 is detected from the rising edges of the two signals, and in accordance with such phase relationship detected, the ratio between the "1" level and the "0" level (ratio between fl and gl) is changed as represented by the gate clock pulses fl and gl of FIG. 3 (d), thereby controlling both the frequency and the phase of the feedback signal P2.
Thus, due to the technique of mutually comparing the rising edges of the target signal P1 and the feedback signal P2 as described above, it becomes possible to obtain an output synchronized with the rectangular signal P1 having a target frequency.
Since the conventional phase-locked loop circuit has such constitution mentioned above, the input signal (rectangular signal P1) is controlled merely once per cycle to consequently raise a problem that a satisfactory follow-up characteristic is not attainable with regard to variations in the input signal P1.